+--------------------------------------------------------+ | SmarTest Workspace | +--------------------------------------------------------+ | +--------------------+--------------------+ | | | +-----------+ +-----------+ +-----------+ | Pin Config| | Timing | | Levels | | (.pin) | | (.tim) | | (.lev) | +-----------+ +-----------+ +-----------+ | | | +--------------------+--------------------+ | v +--------------------------+ | Test Flow Execution Engine| +--------------------------+ File Formats and Directory Structure
By following these recommendations and using the Verigy 93K tester manual as a guide, users can get the most out of their device and achieve high-quality results.
Chain the tests together inside the Test Flow editor to dictate how the device moves from one test block to the next. 5. Coding Custom Test Methods (C++ API Examples)
: Always check the manual for maximum ratings before making connections to prevent fire or shock. Physical Connections verigy 93k tester manual
The (V93K) platform stands as a cornerstone in the semiconductor industry, recognized as a highly scalable System-on-Chip (SoC) test platform designed to handle everything from engineering characterization to high-volume manufacturing. Its documentation serves as the essential roadmap for test engineers, detailing a complex architecture built on "test processor-per-pin" technology. 1. Hardware Architecture and Configuration
An efficient engineer uses the software's built-in debugging toolkit to isolate faults quickly and maximize throughput. Essential Debugging Tools
Building a test program on the 93K is a structured process, well-documented in the system’s "Test Program Development" guides. The flow generally follows these steps: Coding Custom Test Methods (C++ API Examples) :
In the complex world of semiconductor design and manufacturing, the Automatic Test Equipment (ATE) serves as the final arbiter of quality. Among the most prominent platforms in the industry is the Verigy V93000 (often referred to simply as the "93k"). Following Verigy’s acquisition by Advantest, the V93000 solidified its position as a standard for testing System-on-Chip (SoC) and mixed-signal devices. However, the sophistication of the hardware is matched only by the complexity of its operation. The primary interface between the engineer and this machine is the V93000 Tester Manual and its associated software documentation. This essay explores the structure, utility, and challenges of the V93000 manual, arguing that while it is an encyclopedic technical resource, it requires a distinct pedagogical approach to transform from a reference tome into a practical engineering tool.
The test flow is the sequence in which individual test methods are executed. The manual covers:
The manual also covers advanced debugging features such as . ORE allows test developers to "inject" simulated faults into the test program to see how the system handles errors without having a physical DUT. This feature is essential for ensuring test program stability and robust binning strategies. Instead of hard-coding values
Educational summaries like this V93000 Hardware Overview are available on Scribd.
The 93k uses an equation-based timing system. Instead of hard-coding values, engineers use variables to define cycle times and edge placements, allowing for easy frequency scaling during characterization.
license management utility and starting SmarTest in offline mode. Hardware & System Reference Hardware Overview:
The documentation distinguishes between different classes (e.g., A, C, S, and L ), which vary in test head size to match specific pin-count and performance requirements.
Understanding how to configure digital and analog cards for specific device requirements.