Provides timing independent of system clocks.

possible input combinations. For a circuit with 64 inputs, evaluating every state would require 2642 to the 64th power

Flip-flops are chained together to form a massive shift register (Scan Chain). Test patterns are shifted serially into the chip using a single Scan In pin.

The logic synthesis tool, guided by DFT constraints, connects scan flops into balanced chains, respecting physical placement.

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This technique effectively turns a complex sequential circuit into easily testable combinational logic blocks.

Scan flip-flops, BIST controllers, and JTAG routing require physical silicon space. Increases chip size and manufacturing cost per wafer.

Deep sub-micron nodes introduce internal transistor failures that logic-level models miss:

or heuristic state-space searches to automatically create test patterns for complex circuits. Logic and Fault Simulation: